Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
High-level circuit designs are often specified through a graphical user interface (GUI) or hardware description language (HDL) such as VHDL or Verilog. GUIs and HDLs provide a high-level of abstraction when creating a circuit design, which may simplify and expedite the design task. High-level circuit design tools aid in the development of large-scale designs. Different groups may be tasked with creating different parts of a design, and the different parts of the design may be merged at a high level and compiled.
High-level design approaches and parallel development of parts of a design may lead to a design that is inefficient and more expensive than desired. For example, different parts of the design may instantiate physically discrete, fixed size blocks of RAM that are available on the target device. However, many of the memory blocks may be only partially used by the design. That is, the target device may provide fixed-size memory blocks. Yet only a portion of each of those fixed-size memory blocks that is instantiated in the design may be used by the design. For example, a fixed-size memory block may be 1 Mbyte, and the design may need to access only 300 Kbytes of the memory block, leaving 700 Kbytes of unused memory.
Memory blocks that are partially used waste power as the static power consumption of the unused portions of the memory blocks contribute to the overall power consumption of the device even though the unused portions do not contribute to the functioning of the design. Partially used memory blocks may also increase the end-product cost. If the number of memory blocks instantiated in a design exceeds the number of memory blocks available on a single device, the design may need to be split implemented on multiple devices, which may be more expensive than a single device.